Generally, RAM (Random Access Memory) refers to a computer memory unit, which is read and written freely, and is used mainly as a unit on which data is stored temporarily. DRAM (Dynamic Random Access Memory) is a kind of RAM and stored information is diminished as time passes and thus the diminished information has to be reproduced periodically. Meanwhile, DRAM is a simple structure and integrated easily and thus is used as a high-capacity temporary storage device.
DRAM comprises a plurality of word lines, a plurality of bit lines, and a plurality of memory cells which are connected electrically between the word lines and bit lines and have transistors and capacitors wherein capacity of DRAM is determined depending on the number of memory cells within the DRAM chip.
Currently, DRAM has a memory cell size of 8F2 (8F square). Here, minimal processing size (F) of DRAM corresponds to widths of word lines and bit lines and interval between the word line and bit line and area occupied by one memory cell is 8F2 (4F×2F). In order to fabricate high-capacity DRAM, the minimal process size (F) has to become smaller or the memory cell has to be designed or arranged more intensively under a predetermined minimal process size (F). To become the minimal process size (F) smaller meets a physical limitation and thus memory cell size tends to become smaller.
In order to arrange memory cells more intensively DRAMs having memory cell sizes of 6F2 (3F×2F) and 4F2 (2F×2F) have been proposed. Among them DRAM having a memory cell size of 4F2 includes the most intensively arranged memory cell and provides high-capacity DRAM.
FIG. 1 shows cell arrangement in a 4F2 memory cell DRAM. Referring to FIG. 1, memory cells 10 are placed at intersectional points of word lines WL0-WL3 and bit lines BL0-BL3, respectively.
A proposed configuration example of respective memory cell 10 is shown in FIG. 2. Referring to FIG. 2, a bit line BL is located on a lower side of the memory cell and a word line WL intersects the bit line BL and is placed thereabove. Meanwhile, a drain 11 is placed between the word line WL and bit line BL and further a channel 12 and a gate insulating member 13 surrounding the channel 12 are formed on the word line WL above the drain 11. Additionally, a source 14 is placed above the channel 12 and the gate insulating member 13. A capacitor 15 is placed above the source 14 and the upper part of the capacitor 15 is grounded. Here, the drain 11, gate insulating member 13 and source 14 form one transistor and the transistor and the capacitor 15 form one memory cell 10, and thus the memory cell 10 is formed vertically at an intersectional point of the bit line BL and word line WL.
However, DRAM of the 4F2 memory cells has the following problems.
(1) Since the channel 12 and the gate insulating member 13 are formed within the word line WL having a width of the minimal process size F, a fabrication process of DRAM is very difficult and intricate. In addition, resistance and capacitance of the word line WL are increased abruptly by the channel 12 and the gate insulating member 13 and thus an application thereof is difficult.
(2) The drain 11 formed of N+ implanted silicon is formed vertically above the bit line BL which is made of metal, and resistance of the drain is larger than that of the bit line BL. Additionally, in order to form the memory cell 10 including the drain 11 on the bit line BL formed of metal a process of Epi-Growth or poly-silicon crystallization is necessary and in this case leakage control of the memory cell 10 is difficult. As a result, DRAM of 4F2 memory cell has not been widely used regardless of its high integration degree.